In the design process for an integrated circuit, an initial “high-level” description of the circuitry must be converted into a description of an actual physical implementation of the circuitry in silicon. The description of the physical implementation generally includes all of the electronic components (i.e. transistors, diodes, resistors, capacitors, inductors, adders, multipliers, flip-flops, gates, buffers, etc.) and the paths (i.e. electrical conductor traces) for all of the signals between all of the components. Some of these signal paths are for the data that produce the overall function of the integrated circuit. Additionally, some of the signal paths are for one or more clock signals that trigger the function of some of the electronic components, such as flip-flops.
Some of the electronic components must be synchronized with others of the electronic components in order to ensure that these electronic components receive the correct data signals at the right time and produce reliable data output therefrom. Thus the rising and/or falling edges of the clock signals must trigger these electronic components at precisely the right time to synchronize their function. Therefore, a significant part of the design process for the integrated circuit involves analyzing the clock signal paths and components in these paths to determine the arrival time of rising and/or falling edges of the clock signals at the various synchronized electronic components.
During the design process, an initial physical placement is made of “high-level” primary data path and clock path components followed by an optimization of the data path components. In other words, the essential data and clock path electronic components and signal paths between them are placed in the design, but significantly more details in the data path are usually determined before the complete physical placement of the clock path components. Then, when buffers and other detail design components in the clock path are instantiated, their effect on the timing of the clock signals and the data path components' signal arrival time can be determined. The addition of such details (e.g. additional clock path component placement, buffering, etc.) in the clock path is commonly referred to as “clock tree synthesis.”
Clock tree synthesis (CTS) instantiates the clock circuitry or builds a clock buffer tree according to a clock tree specification file, generates a clock tree topology, and balances clock phase delay with inserted clock buffers. Before CTS, the clock timing is in “ideal clock mode.” Ideal clock mode means that it is assumed that there are no delays in the clock signals. In other words, prior to CTS, the initial placement of the primary data and clock path components, along with detailed optimization of the data path, is done without knowing the effect of the clock signals in the design. After the clock tree has been instantiated, however, the clock timing is in “propagated clock mode,” in which delays in the clock signals have been determined. It is, thus, only after the CTS stage of the design process when it is possible to determine whether the clock signals properly synchronize the data path components.
Those clock signals that do not properly synchronize the data path components are said to have clock timing violations, including clock gating setup violations. True clock timing violations can be seen during the design process only after the CTS stage, once the clock timing is in propagated clock mode. Post-CTS data path optimizers can sometimes fix the clock gating setup violations. However, it is often too late during the design process to fix the clock gating setup violations after the CTS stage, because there has typically been a lot of data path optimization that happened before the CTS stage that may have greatly restricted the options for further modifications. Additionally, the clock may be so restricted that the data path optimizers may not fulfill the requirements for data path signal arrival times. Although the pre-CTS optimizers operate on the clock gating setup violations, the pre-CTS optimizers may not even “see” the clock delays and clock gating setup violations, since the clock is in ideal clock mode during that part of the design process.
Additionally, the post-CTS optimizers often cannot fix clock gating setup violations, because such optimizers operate on the data path, rather than on the clock path. Thus, although operations on the data path can affect clock gating setup violations, the post-CTS optimizers are limited by the clock path arrival times. In fact, once the CTS stage is done, the clock tree, or the clock path, is considered to be completed. Modifications to the clock path after the CTS stage generally lead to worse timing violations, because symmetry, or skew, in the clock path usually worsens. Therefore, if a clock path solution has been committed during the CTS stage that is not good for clock gating setup violations, then the post-CTS data path design optimizers will likely not be able to fix these violations. In such a situation, it can be very difficult, if not impossible, for the design process to “converge” on a final design. This problem is often a major bottleneck at this point in the design process.